HyperLink NAND Flash Interface Architectural Specification

Overview

The HyperLink NAND Flash Architecture defines a class of non-volatile memory devices intended for a use in applications with a wide range of performance and cost sensitivities. The principle devices defined by this architecture are NAND Flash devices, known as HyperLink NAND or HLNAND, although the aim of the architecture is to provide compliance with a range of device types capable of operating on a common interface, known as the HyperLink Channel. The HyperLink Architecture balances the width, frequency and latency of the memory-to-controller interconnect (HyperLink Channel) to minimize the pin count, die area, power consumption, and thereby the cost, of the memory devices and the entire memory subsystem. In addition, the architecture is crafted to facilitate the existence of a generic off-the-shelf controller that learns the characteristics of the devices it is controlling at power-on. Finally, it facilitates lates election of the devices being used to populate the memory system by decoupling the physical link characteristics from those of the memories being used.

A HyperLink memory system has a ring topology. A single data link, typically but not necessarily 8 bits wide, is daisy chained from the controller, through the memory devices and back to the controller. It carries addresses, commands and data in variable length, serialized packets. Two strobe signals parallel the data signals to delineate the start and end of command and data packets. For a four-bit link, the total interface, including data, strobes, clocks and power control and reset, requires only 16 signal pins. With a single bit link, the total drops to only 10 signal pins. Consequently, the entire interface can be implemented with a single row of pads across the width of most memory devices...

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