Emerging Solutions Panel at IEEE NVSMW, May 2008

HYPERLINK: A NEW MEMORY INTERFACE FOR MASS STORAGE

Conventional Memory Interface

• Bidirectional, multi-drop bus common to SRAM, DRAM, Flash
• Heavily loaded bus results in reduced bandwidth and high power
• Memory processes such as NAND Flash offer relatively poor transistor performance in driving large loads
• Proliferation of CE signals in mass storage applications like SSD

HyperLink Memory Interface

• Unidirectional, point-to-point, ring topology supports large configurations without performance degradation
• Lightly loaded signals, no stubs or reflections
• Low power due to small pin capacitance
• Increased pin bandwidth more than compensates for increased pin count due to separate input and output
• Device address assigned on initialization — not multiple CE signals

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