HyperLink NAND Flash 256Gb MCP

Introduction

The HLNAND Flash device HL7F256G24DBAA-1W is a next generation flash memory delivering the most advanced capabilities with high performance for a broad range of flash applications.  HLNAND Flash memory, based on NAND flash cell technology, provides the most cost-effective solution for mass storage applications. 


HL7F256G24DBAA-1W is a 256Gb Flash memory device with a single HyperLink interface and quad memory banks each having two separate LUNs (Logical Units).  This device is packaged in an MCP (multi-chip-package), composed of a stack of 9 dies, including eight monolithic 32Gb MLC Toggle Mode NAND Flash chips, evenly distributed over four banks, and one ASIC interface chip.  The interface chip contains the external high-speed HyperLink interface and controls each flash bank automatically and independently.  HL7F256G24DBAA-1W supports an Error Detection Code (EDC) feature to eliminate bit errors in ‘Command Packets’ to ensure reliability and error-free communication of commands and register data.  HL7F256G24DBAA-1W provides user configurable virtual pages for read with the various page depth choices, 2048B, 4096B, 8192B and a full page of 8704B.

Features

•HLNAND MCP w/ 8-NANDs & Interface-Chip
•Fully Compliant HyperLink Interface
HL-266 (DDR 266)
•Simultaneous Read & Write operations
•Supports Error Detection Code (EDC) for Command Packets & Register Read Packets
•Broadcast Status Register Read Command
•Sustained Read/Write Throughput up to 266MB/s
•Differential Clocking (CK and CK#)
•On-the-Fly User Configurable Data Read Virtual Page Sizes (2048, 4096, 8192 or 8704 Bytes)
•Highly Flexible Modular Command Structure
•Bank-Oriented Memory Architecture
•Quad Bank with Dual LUN Architecture
•Supports Concurrent Multi Bank Operations
•Supports Two-LUN per Bank Operations
•Supports Two-Plane per LUN Operations
•Scalable Memory Capacity
•Broadcasting Commands
•Daisy-chain cascade up to 255 number of linked devices to increase memory capacity with undiminished data throughput
•1.8V LVCMOS Compatible IO
•HLNAND MCP w/ 8-NANDs & Interface-Chip
•Fully Compliant HyperLink Interface
HL-266 (DDR 266)
•Simultaneous Read & Write operations
•Supports Error Detection Code (EDC) for Command Packets & Register Read Packets
•Broadcast Status Register Read Command
•Sustained Read/Write Throughput up to 266MB/s
•Differential Clocking (CK and CK#)
•On-the-Fly User Configurable Data Read Virtual Page Sizes (2048, 4096, 8192 or 8704 Bytes)
•Highly Flexible Modular Command Structure
•Bank-Oriented Memory Architecture
•Quad Bank with Dual LUN Architecture
•Supports Concurrent Multi Bank Operations
•Supports Two-LUN per Bank Operations
•Supports Two-Plane per LUN Operations
•Scalable Memory Capacity
•Broadcasting Commands
•Daisy-chain cascade up to 255 number of linked devices to increase memory capacity with undiminished data throughput
•1.8V LVCMOS Compatible IO
•Power Supply
−VCC & VCCQ = 1.8V (HL Interface Chip Logic)
−VCCN & VCCNQ = 3.3V (NAND Flash)
•Organization
−Page Size: (8K + 512) Bytes
−Block Size: 128 Pages = (1M + 64K) Bytes
−Bank Size: 8304 Blocks = (8G + 512M) Bytes
−Device Size: 4 Banks = (32G + 2G) Bytes
•Package
−100-Ball BGA (18 x 14 / 1.0mm pitch)

Documents

Product Brief

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