HyperLink NAND Flash 32Gb MCP

The HL7F32G14CB11-1W is a 32Gb Flash memory device with a single HyperLink interface and quad memory banks. It is composed of 5 stacked chips in an MCP (multi-chip-package), including four monolithic 8Gb SLC NAND Flash chips for each bank, and one ASIC bridge chip to control the independent banks and establish high speed HLNAND interface and protocol. The unified synchronous interface and protocol of HLNAND Flash greatly improves data throughput while supporting feature-rich operation.

HLNAND Flash offers an easy device daisy-chain scheme for virtually unlimited number of linked devices to accommodate system integration with greater expandability and flexibility. The serial interface promises further performance improvement with higher clock rate, better signal integrity and lower power consumption.

Features

• HLNAND Bridge Chip MCP w/ 4-NANDs Stacked

• Fully Compliant HyperLink Interface

HL1-266 (DDR 266)

• Supports Error Detection Code for Command Packets

• Broadcast Status Register Read Command

• Differential Clocking (CK and CK#)

• User Configurable Link width (x1, x2, x4 or x8)

• On-the-Fly User Configurable Data Read and Data

Write/Load Virtual Page Sizes

(128, 256, 512, 1024, 2048, 4096 or 4224 Bytes)

• Highly Flexible Modular Command Structure

• Bank-Oriented Memory Architecture

• Quad Bank Architecture

• Concurrent Bank Operations

- Concurrent Page Read

- Concurrent Page Program

- Concurrent Page Copy

- Concurrent Block Erase

- Read while Program

- Page Copy while Erase

- Program while Erase

• Scalable Memory Capacity

• Broadcasting Commands

• Daisy-chain cascade up to 255 number of linked devices to increase memory capacity with undiminished data throughput

• 1.8V LVCMOS Compatible IO

• Power Supply

- VCC & VCCQ = 1.8V (Bridge Chip Logic)

- VCC3 = 3.3V (NAND Flash Chips)

• Organization

- Page Size: (4K + 128) Bytes

- Block Size: 64 Pages = (256K + 8K) Bytes

- Bank Size: 4096 Blocks = (1G + 32M) Bytes

- Device Size: 4 Banks = (4G + 128M) Bytes

• Automatic Program and Erase

- Page Program: 128 ~ 4224 Bytes

- Block Erase: 64 Pages

• Read Performance

- Random Read: 29μs ~ 131μs (Max.)

- Burst Read: 3.75ns (Min.)

- Pass-through: 7.5ns (Min.)

• Write Performance

- Page Program: 204μs ~ 306μs (Typ.)

- Block Erase: 1.5ms (Typ.)

• Hardware Data Protection (by RST#)

• Program/Erase Lockout During Power Transitions

• Reliable CMOS Floating-Gate Technology

• Endurance:

- 100K Program/Erase Cycles (with 1bit/512Byte ECC)

- Data Retention: 10 Years

• Package

- 100-Ball BGA (18 x 12 / 1.0mm pitch)

Documents

Datasheet PDF login required

Simulation Models

Verilog Model - coming soon