The HyperLink NAND Flash Architecture defines a class of non-volatile memory designs intended for use in applications with a wide range of performance and cost sensitivities.
About HyperLink (HL) Interface Technology
HyperLink (HL) interface was developed to accommodate various memory devices using different cell technology and works within a homogenous or heterogeneous system.
The HL Architecture defines two classes of rings and devices. The corresponding operating modes are denoted HL1 and HL2. HL1 rings have a maximum operating frequency of 133MHz and use LVCMOS signaling and parallel clock distribution. This performance is denoted as HL1-266 to indicate the DDR bit rate. The higher performance HL2 rings use on-chip PLLs, HSTL-1 signaling, and differential source synchronous clocking. It is anticipated that HL2 devices and rings will attain a maximum operating frequency in excess of 400MHz. With a link width of 8 bits, a peak bandwidth of 800MBps will be possible using HL2-800 devices.
- Parallel clock scheme in HL-1
- Source synchronous clock scheme for high speed in HL-2
- Dual capable devices built into the architecture