HLNAND’s patented daisy-ring architecture delivers the SSD industry’s most advanced capabilities for mass storage applications.


HLNAND is built upon a unique daisy-ring architecture that outpaces the parallel bus architecture used in industry standard NAND Flash products.

Controller Diagram

HLNAND delivers superior scalability, performance and reliability over SSDs that use conventional NAND Flash devices.

Interface Diagram
  • HLNAND MCP w/ 4,8,16-NANDs & Interface-Chip
  • Fully Compliant HyperLink DDR Interface
    • HL-266/HL-333/HL-400
    • HL-533/HL-667/HL-800
  • Supports Error Detection for Command Packets (CRC-8)
  • Sustained Read/Write Throughput up to 800MB/s
  • Source Synchronous Clocking (CK and CK#)
  • Highly Flexible Modular Command Structure
  • Bank-Oriented Memory Architecture
  • Quad Bank with Quad LUN Architecture (Max)
  • Supports Multi-Bank Interleaving Operations
  • Supports Multi-LUN Interleaving Operations
  • Supports Multi-Plane Operations
  • Scalable Memory Capacity
  • Broadcasting Feature
  • Daisy-chain cascade up to 255 number of linked devices to increase memory capacity with undiminished data throughput
  • Supports Read Retry operation
  • JEDEC Standard 1.2V, HSUL_12 Unterminated Interface
  • Power Supply
    • VCC / VCCQ = 1.2V / 1.2V (Interface Chip)
    • VCCN / VCCNQ = 3.3V / 1.8V (NAND Flash)
  • Automatic Program and Erase
    • Page Program: (8K + 640) Bytes
    • Block Erase: (1M + 80K) Bytes
  • Read Performance
    • Random Read: 80μs (Max.)
    • Burst Read: 1.875ns/1.5ns/1.25ns (Min.)
    • Pass-through: 3.75ns/3.0ns/2.5ns (Min.)
  • Write Performance
    • Page Program: 1.3ms (Typ.)
    • Block Erase: 5ms (Typ.)
  • Package
    • 132-Ball BGA (18 x 12 / 1.0mm pitch)
    • 152-Ball BGA (18 x 14 / 1.0mm pitch)